1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more specifically, it relates to a nonvolatile semiconductor memory device rewriting stored information by polarization reversal of a ferroelectric material.
2. Description of the Prior Art
A nonvolatile ferroelectric memory rewriting stored information by polarization reversal of a ferroelectric material is generally referred to as an FRAM (ferroelectric random access memory). Memory cells of such an FRAM are roughly classifiable into two types of structures.
In the first structure of a DRAM (dynamic random access memory) type, charges are stored in a storage capacitor as information. In this structure, memory cells formed by ferroelectric capacitors and switching transistors are arranged in the form of a matrix for performing addressing with a bit line and a word line connected to each transistor and detecting charges following inversion of polarization as shown in FIG. 65. The operation principle of an FRAM memory cell having such a structure is as follows:
As shown in FIG. 66, the relation between a polarization value B of the ferroelectric capacitor and an applied voltage V draws a hysteresis loop. In a nonvolatile operation, information is stored in points A and B of two states under an applied voltage xe2x80x9c0 Vxe2x80x9d. It is assumed here that the polarization state of the storage capacitor is at the point A. The polarization value moves to a point C when applying 5 V and 0 V to a plate line and the bit line respectively, and returns to the point A when returning the applied voltage to 0 V. However, the polarization value moves to a point D due to polarization inversion when applying 0 V and 5 V to the plate line and the bit line respectively, and moves to the point B after returning the applied voltage to 0 V. This indicates that the stored information is rewritten from the point A to the point B. Thus, the storage state can be rewritten by changing the voltages applied to the plate line and the bit line for externally determining the stored information as a polarization current.
In the second structure of an FET (field-effect transistor) type, a silicon oxide film forming a gate insulator film of a general MOS (metal oxide semiconductor) FET is replaced with a ferroelectric film as shown in FIG. 67, and this structure is referred to as an MFSFET. An MFSMISFET type memory cell formed by inserting a floating gate between a gate electrode and a channel as shown in FIG. 68 is also proposed as a modification of this structure.
In each of the first and second structures, a single type of ferroelectric material is generally employed for the FRAM.
When the stored information is rewritten a number of times in the FRAM, however, a hysteresis characteristic is deteriorated to educe the quantity of read charges. Further, dispersion of hysteresis characteristics of ferroelectric capacitors in large-scale memory cells, particularly dispersion in coercive filed results in write and read failures. Thus, the FRAM has such disadvantages that stable operations of writing and reading stored information cannot be attained, the FRAM must be driven with a sufficient write voltage, and a drive time and a drive voltage are limited.
FIG. 69 shows memory cells of a 2T2C system provided for overcoming such disadvantages. In the 2T2C system, complementary signals from two memory cells in which data are complementarily written are input as two differential inputs in a sense amplifier for detecting the data. Therefore, two storage capacitors of a single memory cell are subjected to writing by the same number of times, and hence ferroelectric films are equally deteriorated to enable stable operations. In this case, however, the memory cell area is doubled to disadvantageously increase the chip area.
In order to prevent dispersion in coercive filed, the thickness of ferroelectric films may be reduced. In this case, however, voltage resistance across electrodes is reduced to disadvantageously cause dielectric breakdown.
While a single ferroelectric film is generally held between a pair of electrodes in the structure of a ferroelectric capacitor, a multilayer structure of a ferroelectric film and another film may be held between a pair of electrodes as follows:
When a ferroelectric film directly comes into contact with a silicon substrate in an FET type memory cell, it is difficult to stably operate a transistor due to occurrence of a trap level or formation of a dielectric material such as SiO2 on the surface of the silicon substrate. Therefore, a multilayer structure of a dielectric film and a ferroelectric film may be employed on a silicon substrate. In this case, however, the dielectric film is a paraelectric material operating as a capacitor having no hysteresis characteristic, and does not overcome the aforementioned disadvantages such as dispersion in coercive filed.
For example, Japanese Patent Laying-Open No. 5-259391 (1993) discloses a structure obtained by stacking ferroelectric films. This gazette shows a structure obtained by stacking three ferroelectric films 103a, 103b and 103c between a bottom electrode 102 and a top electrode 104, as shown in FIG. 70. While the aforementioned gazette states that random defects of thin films are effectively reduced due to the multilayer structure of the ferroelectric films 103a, 103b and 103c, this structure does not overcome the aforementioned disadvantages such as dispersion in coercive filed.
Japanese Patent Laying-Open No. 7-14380 (1995) shows a structure obtained by connecting a ferroelectric capacitor 110 formed by a pair of electrodes 111 and 113 and a ferroelectric film 112 in parallel or series with a ferroelectric capacitor 120 formed by a pair of electrodes 121 and 123 and a ferroelectric film 122, as shown in FIGS. 71A or 71B. While the aforementioned gazette states that a composite hysteresis characteristic shown in FIG. 72 is obtained due to this structure thereby implementing nondestructive reading and avoiding characteristic deterioration, this structure does not overcome the aforementioned disadvantages such as dispersion in coercive filed either.
Japanese Patent Laying-Open No. 7-14380 also states that three values can be stored by adjusting hysteresis characteristics of two ferroelectric films and obtaining a composite hysteresis characteristic shown in FIG. 73.
An object of the present invention is to provide a nonvolatile semiconductor memory device capable of suppressing dispersion in coercive filed and preventing reduction of voltage resistance without increasing the chip area.
Another object of the present invention is to provide a nonvolatile semiconductor memory device storing at least four values by changing a drive system for memory cells dissimilarly to the system described in Japanese Patent Laying-Open No. 7-14380.
According to the present invention, a nonvolatile semiconductor memory device rewriting stored information with a quantity of charges of a dielectric material comprises a ferroelectric film having a hysteresis characteristic in a dependency of an electric flux density D and an electric field E and a nonlinear element electrically connected with the ferroelectric film and having at least either such a characteristic that the quantity of increase of a positive electric flux density D with respect to the electric field E is small in a low electric field region and large in a high electric field region in the dependency of the electric field density D and the electric field E or such a characteristic that the quantity of increase of a positive current I is small in a low electric field or low voltage region and large in a high electric field or high voltage region in a dependency of the current I and the electric field E or an applied voltage V.
According to the inventive nonvolatile semiconductor memory device, the nonlinear element has a small quantity of increase of the positive electric flux density D with respect to the electric field E in the low field region and hence an electric field acting on the ferroelectric film is small and suppresses polarization inversion of the ferroelectric film in the low field region. In the high field region, on the other hand, the nonlinear element has a large quantity of increase of the electric flux density D with respect to the electric field E and hence the electric field acting on the ferroelectric film abruptly increases and prompts polarization inversion of the ferroelectric film in the high field region. Thus, polarization inversion of the ferroelectric film is abruptly prompted in the high field region and hence, also when the ferroelectric film is dispersed in coercive filed, the nonlinear element suppresses such dispersion for stabilizing a read/write operation of a memory cell.
The nonlinear element has a small quantity of increase of the positive current I with respect to the electric field E or the applied voltage V in the low field or low voltage region and hence an electric field or a voltage acting on the ferroelectric film is small and suppresses polarization inversion of the ferroelectric film in the low field or low voltage region. In the high field or high voltage region, on the other hand, the nonlinear element has a large quantity of increase of the current I with respect to the electric field E or the applied voltage V and hence the current I flowing in the ferroelectric film abruptly increases and prompts polarization inversion of the ferroelectric film in the high field or high voltage region. Thus, polarization inversion of the ferroelectric film is abruptly prompted in the high field or high voltage region and hence, also when the ferroelectric film is dispersed in coercive filed, the nonlinear element suppresses such dispersion for stabilizing the read/write operation of the memory cell similarly to the above.
Also when reducing the thickness of the ferroelectric film for reducing dispersion in coercive filed of the ferroelectric film, the nonlinear element can keep the space between electrodes at a prescribed value. Thus, it is possible to prevent dielectric breakdown caused by excess reduction of the space between the electrodes.
The nonlinear element may simply be stacked on the ferroelectric film, whereby the chip area is not increased.
In the aforementioned nonvolatile semiconductor memory device, the nonlinear element is preferably a dielectric material having a double hysteresis characteristic. Dispersion in coercive filed can be suppressed and dielectric breakdown can be prevented without increasing the chip area by stacking the dielectric material having a double hysteresis characteristic on the ferroelectric film.
In the aforementioned nonvolatile semiconductor memory device, the nonlinear element is preferably an antiferroelectric material. Also in this case, dispersion in coercive filed can be suppressed and dielectric breakdown can be prevented without increasing the chip area.
In the aforementioned nonvolatile semiconductor memory device, the nonlinear element is preferably a ferroelectric material in a paraelectric phase. Also in this case, dispersion in coercive filed can be suppressed and dielectric breakdown can be prevented without increasing the chip area.
Preferably, the aforementioned nonvolatile semiconductor memory device is capable of storing at least four values. Thus, storage of at least four values in a single memory cell can be implemented by combining the ferroelectric film and the nonlinear element with each other.
Preferably, the aforementioned nonvolatile semiconductor memory device has a structure capable of applying at least two voltage pulses of different values to the ferroelectric film and the nonlinear element. Thus, at least four values can be stably stored.
In the aforementioned nonvolatile semiconductor memory device, the nonlinear element is preferably a varistor. Thus, dispersion in coercive filed can be suppressed and dielectric breakdown can be prevented without increasing the chip area by stacking the varistor on the ferroelectric film.
In the aforementioned nonvolatile semiconductor memory device, the nonlinear element is preferably an element having a nonlinear voltage dependency of a current. Thus, dispersion in coercive filed can be suppressed and dielectric breakdown can be prevented without increasing the chip area by stacking the element having the nonlinear voltage dependency of the current on the ferroelectric film.
In the aforementioned nonvolatile semiconductor memory device, the nonlinear element preferably has at least two films electrically connected with the ferroelectric film and having such a characteristic that the quantity of increase of a positive electric flux density D with respect to an electric field E is small in a low electric field region and large in a high electric field region in a dependency of the electric field density D and the electric field E or such a characteristic that the quantity of increase of a positive current I is small in a low field or low electric voltage region and large in a high electric field or high voltage region in a dependency of the current I and the electric field E or an applied voltage. Also in this case, dispersion in coercive filed can be suppressed and dielectric breakdown can be prevented without increasing the chip area.
The nonvolatile semiconductor memory device preferably further comprises an insulated gate field-effect transistor and a capacitor electrically connected with one of a pair of source/drain regions of the insulated gate field-effect transistor, and the ferroelectric film and the nonlinear element are preferably held between a pair of electrodes included in the capacitor. Thus, the present invention is applicable to a DRAM type FRAM memory cell.
The aforementioned nonvolatile semiconductor memory device preferably further comprises an insulated gate field-effect transistor, and the ferroelectric film and the nonlinear element are preferably held between a region held between a pair of source/drain regions of the insulated gate field-effect transistor and a control gate electrode. Thus, the present invention is applicable to an MFSFET type FRAM memory cell.
The aforementioned nonvolatile semiconductor memory device preferably further comprises an insulated gate field-effect transistor. The insulated gate field-effect transistor has a pair of source/drain regions and a floating gate electrode and a control gate electrode formed on a region held between the pair of source/drain regions, and the ferroelectric film and the nonlinear element are held between the control gate electrode and the floating gate electrode. Thus, the present invention is applicable to an MFMISFET type FRAM memory cell.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.